1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com hv310 features pwrgd = active low -10v to -90v input voltage range few external components 0.33ma typical standby supply current programmable over/under voltage limits with hysteresis programmable current limit active control during all phases of start-up programmable timing 8-lead soic package applications central of?ce switchingservers pots line cards isdn line cards xdsl line cards pbx systems powered ethernet for voip distributed power systems negative power supply control antenna and ?xed wireless systems ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? general description the supertex hv310, hotswap controller, negative supply controls the power supply connection during insertion of cards or modules into live backplanes. it may be used in traditional negative 48v powered systems or for higher voltage busses up to negative 90v. operation during the initial power up prevents turn-on glitches, and after complete charging of load capacitors (typically found in ?lters at the input of dc-dc converters) the hv310 issues a power good signal. this signal is typically used to enable the dc-dc converter. once a pwrgd signal has been established, the device sleeps in a low power state, important for large systems with many individual hotswap cards or modules. an external power mosfet is required as the pass element, plus a ramp capacitor, and resistors to establish current limiting and over and under voltage lockouts. there is no need for additional external snubber components. features are programmable over voltage and under voltage detection of the input voltage which locks out the load connection if the bus (input) voltage is out of range. an internal voltage regulator creates a stable reference, and maintains accurate gate drive voltage. the unique control loop scheme provides full current control and limiting during start up. theory of operation initially the external n-channel mosfet is held off by the gate signal, preventing an input glitch. after a delay (while internal circuits are activated) the inrush current to the load is limited by the gate control output. the current may ramp up and limit at a maximum value programmed by an external resistor. initial time delay, to allow for contact bounce, and charging operation is determined by the single external ramp capacitor connected to the ramp pin. when the load capacitor is fully charged, the controller emerges from current limit mode, an additional time delay occurs before the external n- channel mosfet pass transistor is switched to full conduction, and the pwrgd output signal is activated. the controller will then transition to a low power standby mode. typical application circuit hotswap, inrush current limiter controllers (negative supply rail) vdd uv ov vee sense gate -48v r4 50m r1 487k r2 6.81k r3 9.76k q1 irf530 c load +5v hv310 8 32 4 7 com dc/dc pwm converter 1 gnd pwrgd enable 5 ramp 6 c1 10nf gnd long pin short pin jumper long pin notes: 1. undervoltage shutdown (uv) set to 35v. 2. overvoltage shutdown (ov) set to 65v. 3. remove jumper if short pin is used. downloaded from: http:///
2 hv310 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com ordering information device package option 8-lead soic 4.90x3.90mm body 1.75mm height (max) 1.27mm pitch hv310 HV310LG-G -g indicates package is rohs compliant (green) absolute maximum ratings parameter value v ee referenced to vdd pin +0.3 to -100v v pwrgd referenced to v ee voltage -0.3 to +100v operating ambient temperature -40c to +85c operating junction temperature -40c to +125c storage temperature -65c to +150c uv and ov referenced to v ee -0.3 to +12v absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. pin con?guration sym parameter min typ max units conditions supply (referenced to vdd pin) v ee supply voltage -90 - -10 v --- i ee supply current - 550 650 a v ee = -48v, mode = limiting standby mode supply current - 330 400 a v ee = -48v, mode = standby ov and uv control (referenced to vee pin) v uvh uv high threshold - 1.26 - v low to high transition v uvl uv low threshold - 1.16 - v high to low transition v uvhy uv hysteresis - 100 - mv --- v ovh ov high threshold - 1.26 - v low to high transition v ovl ov low threshold - 1.16 - v high to low transition v ovhy ov hysteresis - 100 - mv --- electrical characteristics (v in = -10 to -90v, -40c t a +85c unless otherwise noted) y = last digit of year sealed ww = week sealed l = lot number = green packaging yww hv310 l l l l 8-lead soic (lg) (top view) product marking 12 3 4 87 6 5 pwrgd ov uv vee vdd ramp gate sense 8-lead soic (lg) package may or may not include the following marks: si or downloaded from: http:///
3 hv310 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com sym parameter min typ max units conditions current limit (referenced to vee pin) v sense current limit threshold voltage 40 50 60 mv v uv = v ee + 1.9v, v ov = v ee + 0.5v gate drive output (referenced to vee pin) v gate maximum gate drive voltage 9.0 10 11 v v uv = v ee + 1.9v, v ov = v ee + 0.5v i gateup gate drive pull-up current 500 - - a v uv = v ee + 1.9v, v ov = v ee + 0.5v i gatedown gate drive pull-down current 40 - - ma v uv = v ee , v ov = v ee + 0.5v timing control (test conditions: c =100f, c ramp = 10nf, v uv = v ee +1.9v, v ov = v ee +0.5v, external mosfet is irf530 3 ) i ramp ramp pin output current - 10 - a v sense = 0v t por time from uv to gate turn on 1 2.0 - - ms --- t rise time from gate turn on to v sense limit 400 - - s --- t limit duration of current limit mode - - 5.0 ms --- t pwrgd time from current limit to pwrgd - 5.0 - ms --- v ramp voltage on ramp pin in current limit mode 2 - 3.6 - v --- power good output (referenced to vee pin) v pwrgd power good pin breakdown voltage 90 - - v --- power good pin output low voltage - 0.5 0.8 v i pwrgd = 1.0ma dynamic characteristics t gatehlov ov delay - - 500 ns --- t gatehluv uv delay - - 500 ns --- electrical characteristics (v in = -10 to -90v, -40c t a +85c unless otherwise noted) notes this timing depends on the threshold voltage of the external n-channel mosfet. the higher its thresh old is, the longer this timing. this voltage depends on the characteristics of the external n-channel mosfet. v gs(th) = 3.0v for an irf530. irf530 is a registered trademark of international recti?er. 1.2. 3. waveforms drain 50v/div v in 50v/div gate 5.0v/div i inrush 500ma/div 5.0ms/div pwrgd logic device condition pwrgd hv310 not ready 1 hi z ready 0 v ee downloaded from: http:///
4 hv310 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com timing diagram gnd -48v v in i in t start contact bounce i lim pwrgd v uvl t rise t pwrgd v gate initialization limiting full on v gate v out t lim t th v ramp v ramp v gate inactive active v out v in v gs(th) v gs(lim) v ee t por functional block diagram logic v int vdd uv ov vee sense gate ramp v ref uvlo and por band gap reference internal supply regulator v int 5k v int - 1.2v switch v ref 2v ref transconductor buffer pwrgd + - 10ma c c c a c automatic restart delay circuit breaker 100mv note: v int is the internally regulated supply voltage and can range from 9.0 to 11v. v gs(th) is the gate threshold voltage of the external pass transistor and may be obtained from its datasheet. v gs(lim) is the pass transistor gate-source voltage required to obtain the limit curent. it is dependent on the pass transistors characteristics and may be obtained from the transfer characteristics curves on the transistor datasheet.g fs is the transconductance of the pass transistor and may be obtained from its datasheet. r fb is the internal feedback resistor and is 5.0k? nominal. 1.2. 3. 4. 5. i lim = v sense r sense t start = 12v c ramp i ramp t th = v gs(th) c ramp i ramp t por = t start + t th t rise c ramp g fs i ramp - r sense 0.9i lim r fb t lim v in c load - 1 t rise i lim 2 t pwrgd = (v int - v gs(lim) - 1.2v) c ramp i ramp downloaded from: http:///
5 hv310 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com functional descriptioninsertion into hot backplanes telecom, data network and some computer applications require the ability to insert and remove circuit cards from systems without powering down the entire system. all cir- cuit cards have some ?lter capacitance on the power rails, which is especially true in circuit cards or network terminal equipment utilizing distributed power systems. the insertion can result in high inrush currents that can cause damage to connector and circuit cards and may result in unacceptable disturbances on the system backplane power rails. the hv310 was designed to allow the insertion of these cir- cuit cards or connection of terminal equipment by eliminat- ing these inrush currents and powering up these circuits in a controlled manner after full connector insertion has been achieved. the hv310 is intended to provide this function on a negative supply rail in the range of -10 to -90v. operation on initial power application an internal regulator seeks to pro- vide 10v for the internal ic circuitry. until the proper internal voltage is achieved all circuits are held reset, the open drain pwrgd signal is hi-z to inhibit the start of any load circuitry and the gate to source voltage of the external n-channel mosfet is held low. once the internal under voltage lock out (uvlo) has been satis?ed, the circuit checks the input supply voltage under voltage (uv) and over voltage (ov) sense circuits to ensure that the input voltage is within ac- ceptable programmed limits. these limits are determined by the selected values of resistors r1, r2 and r3, which form a voltage divider. assuming the above conditions are satis?ed and while con- tinuing to hold the pwrgd output inactive and the external mosfet gate voltage low, the current source feeding the ramp pin is turned on. the external capacitor connected to it begins to charge, thus starting an initial time delay deter- mined by the value of the capacitor. if an interruption of the input power occurs during this time (i.e. caused by contact bounce) or the ov or uv limits are exceeded, an immedi- ate reset occurs and the external capacitor connected to the ramp pin is discharged. when the voltage on the ramp pin reaches an internally set voltage limit, the gate drive circuitry begins to turn on the external mosfet; allowing the current to softly rise over a period of a few hundred micro-seconds to the current limit set point. while the circuit is limiting current, the voltage on the ramp pin will be ?xed. depending on the value of the load capacitance and theprogrammed current limit, charging may continue for some time. the magnitude of the current limit is programmed by comparing a voltage developed by a sense resistor connect- ed between the vee and sense pins to 50mv (typical). once the load capacitor has been charged, the current will drop which will cause the ramp voltage to continue rising; providing yet another programmed delay. when the ramp voltage is within 1.2v of the internally regu- lated voltage, the controller will force the gate full on and will pull the pwrgd pin low and the circuit will transition to a low power standby mode. the pwrgd pin is often used as an enable for downstream dc/dc converter loads. at any time during the start up cycle or thereafter, crossing the uv and ov limits (including hysteresis) will cause an im- mediate reset of all internal circuitry. thereafter the start up process will begin again. application information under voltage and over voltage detection the uv and ov pins are connected to comparators with nominal 1.21v thresholds and 100mv of hysteresis (1.21v 50mv). they are used to detect under voltage and over voltage conditions at the input to the circuit. whenever the ov pin rises above its threshold or the uv pin falls below its threshold the gate voltage is immediately pulled low, the pwrgd signal is deactivated and the external capacitor connected to the ramp pin is discharged. the under voltage and over voltage trip points can be pro- grammed by means of the three resistor divider formed by r1, r2 and r3. since the input currents on the uv and ov pins are negligible the resistor values may be calculated as follows: uv off = v uvh = 1.16 = |v eeuv | ? (r2+r3) / (r1+r2+r3) ov off = v ovl = 1.26 = |v eeov | ? r3 / (r1+r2+r3) where |v eeuv | and |v eeov | are under & over voltage set points. if we select a divider current of 100a at a nominal operating input voltage of 50v then: (r1+r2+r3) = 50v / 100a = 500k? downloaded from: http:///
6 hv310 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com from the second equation for an over voltage set point of 65v, the value of r3 may be calculated. ov off = 1.26 = 65 ? r3 / 500k? r3 = (1.26 ? 500k) / 65 = 9.69 k? the closest 1% value is 9.76k?. from the ?rst equation for an under voltage set point of 35v, the value r2 can be calculated. uv off = 1.16 = 35 ? (r2 + r3) / 500k r2 = (1.16 ? 500k) / 35 C 9.76k? = 6.81k?.the closest 1% value is 6.81k?. then r1 = 500k C (r2 + r3) = 483k?the closest 1% value is 487k?. undervoltage/overvoltage operationcurrent limit the current limit magnitude above which the current will not be allowed to rise during startup is programmed using a sense resistor connected from the sense pin to vee pin. for example to program a current limit of 1.0a, one would choose a resistor as follows: r sense = 50mv / i sense r sense = 50mv / 1.0a r sense = 50m? gnd v in pass transistor off on uv off uv on ov off ov on pin # function description 1 pwrgd ths pin is held in hi-z state on initial power application and pulls low when the external mosfet is fully turned on. this pin may be used as an enable control when connected directly to a pwm power module. 2 ov this pin, when raised above its high threshold, will immediately cause the gate pin to be pulled low. the gate pin will remain low until the voltage on this pin falls below the low threshold limit, initiating a new start-up cycle. 3 uv this under voltage sense pin, when below its low threshold limit will ensure that the gate pin is low. the gate pin will remain low until the voltage on this pin rises above the high threshold, initializing a new start-up cycle. 4 vee this pin is the negative voltage power supply input to the circuit. 5 vdd this pin is the positive voltage power supply input to the circuit. 6 ramp this pin provides a current output so that a timing ramp voltage is generated when a capacitor is connected. the initial portion of the ramp provides a time delay, which in conjunction with the un- der voltage detection circuit eliminates circuit card insertion contact bounce. the ramp pin also controls the delay between the current limit mode disengaging and the pwrgd signal activating; as well as the current rise pro?le after the initial turn on delay. 7 gate this is the gate driver output for the external n-channel mosfet. 8 sense the current sense resistor connected from this pin to vee pin programs the current limit. constant current output mode is established when the voltage drop across this resistor reaches 50mv. pin description downloaded from: http:///
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receive s an adequate product liability indemnification insuran ce agreement. supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for p ossible omissions and inaccuracies. circuitry and s pecifications are subject to change without notice. for the lates t product specifications refer to the supertex inc. website: http//www.supertex.com. ?2009 all rights reserved. unauthorized use or reproduct ion is prohibited. 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com 7 hv310 (the package drawings in this data sheet may not re?ect the most current speci?cations. for the late st package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp-hv310 a030509 8-lead soic (narrow body) package outline (lg) 4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch 1 8 seating plane gauge plane l l1 l2 e e1 d e b a a2 a1 seating plane a a top view side view view b view b 1 note 1 (index area d/2 x e1/2) view a-a h h note 1 symbol a a1 a2 b d e e1 e h l l1 l2 1 dimension (mm) min 1.35* 0.10 1.25 0.31 4.80* 5.80* 3.80* 1.27 bsc 0.25 0.40 1.04 ref 0.25 bsc 0 o 5 o nom - - - - 4.90 6.00 3.90 - - - - max 1.75 0.25 1.65* 0.51 5.00* 6.20* 4.00* 0.50 1.27 8 o 15 o jedec registration ms-012, variation aa, issue e, sept. 2005. * this dimension is not speci?ed in the original jedec drawing. the value listed is for reference o nly. drawings are not to scale. supertex doc. #: dspd-8solgtg, version h101708. note: this chamfer feature is optional. a pin 1 identi?er must be located in the index area indicated. the pin 1 identi?er can be: a molded mark/identi?er; an embedded metal marker; or a printed indicator. 1. downloaded from: http:///
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